1. Field of the Invention
The present invention relates to a semiconductor memory, more particularly, relates to a FIFO (First-In First-Out) semiconductor memory with plural input ports of a semiconductor integrated circuit.
2. Description of the Related Art
Conventionally, as this technique, DOI and YAMADA disclose "Method of fabricating 160 Gbit/s ATM (Asynchronous Transfer Mode) switch using a variable link speed switch" on 31-33 pages in SSE93-69 of Singaku Giho by Electronic Information Communication Society (Corporation).
As to a FIFO (First-In First-Out) memory with plural input ports, a structural sample is given of an 8W1R multi-port memory used as a buffer memory for an output buffer type ATM (Asynchronous Transfer Mode) switch.
FIG. 14 is a structural view showing a conventional FIFO memory with plural input ports. FIG. 15 is a structural view showing a memory core. FIG. 16 is a structural view showing a write address generator. FIG. 17 is a structural view showing a read address generator.
First, as shown in FIG. 14, the conventional FIFO memory having plural input ports is provided with input data signal multiplexers MUX 1, MUX 2, write request signal multiplexers MUX 3, MUX 4, a write address generator WAG, a memory core RAMCORE, a read address generator RAG, a timing generator TG, and a PLL circuit PLL.
As shown in FIG. 15, the memory core RAMCORE is provided with a memory array MARRAY (2W1R cell, m-word.times.n-bit), write buffers WDB0, WDB1, a sense amplifier SA, an output data latch OLA, write address latches WAL0, WAL1, a read address latch RAL, a write timing control WTC, and a read timing control RTC. The memory core RAMCORE constitutes 2W1R multi-port memory of m-word.times.n-bit.
The write address generator WAG, as shown in FIG. 16, is a logic circuit consisting of and provided with ANDs (AND circuits), an ORs (OR circuits), INVs (inverter circuits), DFFs (D type flip-flops) and SELs (selectors).
The read address generator RAG, as shown in FIG. 17, consists of a shift register in which the DFFs are serially connected.
An explanation is given of an operation of the 8W1R multi-port memory shown in FIG. 14 with reference to FIGS. 18 and 19.
The 8W1R multi-port memory functions to write data of n-bit into each of 8 or under ports simultaneously. As the memory core, a 2W1R multi-port memory of which buffer capacity is m is used. By four-multiplexing write data, the 8W1R multi-port memory is carried out. Further, the PLL produces high-speed clocks, thereby controlling internal timing.
Next, detailed explanations are given of the operation.
First, as shown in FIG. 18, in the write operation, n-bit input data signals WDI7, WDI5, WDI3, WDI1 are four-multiplexed by the MUX 1, n-bit input data signals WDI6, WDI4, WDI2, WDI0 are four-multiplexed by the MUX 2, write request signals WEI7, WEI5, WEI3, WEI1 are four-multiplexed by the MUX 3, and write request signals WEI6, WEI4, WEI2, WEI0 are four-multiplexed by the MUX 4. Four parallel signals of frequency f are time divisional multiplexed into one serial signal of frequency 4f.
The multiplexed n-bit input data signals WDI7, WDI5, WDI3, WDI1, the multiplexed n-bit input data signals WDI6, WDI4, WDI2, WDI0, the multiplexed write request signal WEI7, WEI5, WEI3, WEI1, and the multiplexed write request signals WEI6, WEI4, WEI2, WEI0 are inputted into WD1, WD0, WE1, WE0 in the memory core RAMCORE which is a 2W1R multi-port memory. Simultaneously, the write request signals WEI7, WEI5, WEI3, WEI1 and the write request signal WEI6, WEI4, WEI2, WEI2, WEI0 are inputted into the write address generator WAG.
Thereafter, the write address generator WAG generates write address, and the write address is inputted into WA1, WA0 of the memory core RAMCORE, thereby writing n-bit input data signals WDI7, WDI5, WDI3, WDI1 and n-bit input data signal WDI6, WDI4, WDI2, WDI0.
In the memory core RAMCORE shown in FIG. 15, by the write control clock WCLK and the write timing control WTC outputted from the timing generator TG, data and addresses are respectively outputted from the write buffers WDB0, WDB1 and the write address latches WAL0, WAL1 and are written in the 2W1R cell.
Further, as to write address generated by the write address generator WAG, it is necessary (1) that different addresses are inputted into the respective ports while writing (since a 2W1R multi-port memory is used as the memory core RAMCORE), (2) that an address is inputted into a port which requires to write, and (3) that, since three conditions for sequential access are required to carry out the FIFO function, when the number of write requests is 0 or when the number of shifts is 0 and the number of write requests is 1, a point shifting by +1 is address-inputted into the RAMCORE port which requests (hereinafter, called an internal port), and when the number of write requests is 2, a point shifting by +1 and a point shifting by +2 are respectively address-inputted into the internal port 0 and the internal port 1 simultaneously.
Explanations are given with reference to the timing chart in FIG. 18. In the first cycle of clock CLk, as to ports of the 8W1R multi-port (hereinafter, called an external port), write requests are given to eight ports of the external ports 7-0 simultaneously. As addresses inputted to the memory core RAMCORE, points shifting by +1, +2 are respectively inputted to the internal ports 1, 0 simultaneously.
In the second cycle of clock, write requests are given from four external ports 7, 4, 1, 0 simultaneously. For the external port 7, 8 shifting by +1 compared with the pre-shifted point (7 in WA1) is given to the WA1. For the external port 4, 9 shifting by +1 compared with the pre-shifted point (8 in WA1) is give to the WA0. For the external ports 0 and 1, 10 shifting by +1 compared with the pre-shifted point (9 in WA0) is given to the WA0 and 11 shifting by +2 is given to the WA0. Control of this write address is carried out by the write address generator shown in FIG. 16.
Successively, an explanation is given of read operation. As shown in FIG. 19, data written in the memory core RAMCORE is read by the read address generator consisting of a shift register.
In addition, timings of the write and read operations are controlled by internal high-speed clock .phi..sub.i (i:integer) generated by forming logic in the timing generator TG based on polyphase pulse outputted from the PLL circuit PLL. RST is a signal resetting address outputs from the write address generator WAG and the read address generator RAG.
However, in the above-described conventional structure, since a 2W1R multi-port memory is used for the conventional memory core as shown in FIG. 15, it is necessary to fabricate the write address generator WAG performing complicated control by using a lot of gates as shown in FIG. 16. Therefore, there is a problem that layout area increases.